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Video ICs
SECAM chroma signal processor for VHS VCRs
BA7207AS / BA7207AK
The BA7207AS and BA7207AK are LSI components that incorporate the contain circuitry required for SECAM chroma signal processing. The ICs have both recording and playback systems and each includes a bell filter, a bandpass filter, a limiter amplifier, a multiply-by-four circuit, a divide-by-four circuit, and a sync-gate circuit.
*ApplicationsVHS format video cassette recorders and SECAM and
camcorders
*Features required for SECAM chroma signal pro1) All filters
cessing are provided. 2) Built-in chroma killer circuit.
3) Built-in switch circuit for selecting PAL chroma or SECAM chroma for the PB / REC system output.
*Absolute maximum ratings (Ta = 25C)
Parameter Power supply voltage Power dissipation Operating temperature Storage temperature BA7207AS BA7207AK BA7207AS BA7207AK Symbol VCC Pd Limits 7 1400 (SDIP32)1 850 (QFP44)2 - 25 ~ + 75 - 25 ~ + 65 - 55 ~ + 125 Unit V mW C C
Topr Tstg
1 Reduced by 14mW for each increase in Ta of 1C over 25C . 2 When mounted on a 70mm x 70mm, t = 1.6mm glass epoxy board, reduced by 8.5W for each increase in Ta of 1C over 25C.
*Recommended operating conditions (Ta = 25C)
Parameter Operating power supply voltage Symbol VCC Min. 4.5 Typ. 5.0 Max. 5.5 Unit V
1
Video ICs
BA7207AS / BA7207AK
*Block diagram
PALRIN RECOUT
BA7207AS (SDIP32)
VREG TRAP
ABELO
CREF1
CREF2
CREF3
RECH
x 4O
PBIN
LAIN
32
31
30
29
28
27
26
25
24
23
22
21
MODE CONTOROL
20
19
18
17
VREG
PAL SCM
LIM
x2
2.2MHz BPF
x2
LIM
P
R EQ
P
1.1MHz BPF
R
P R
4.3MHz BPF--A
R
P
BELL
4.3MHz BPF - B
PB SYNC GATE
P
R
/4
REC SYNC GATE
R P
DET VCO
SCM PAL
FREQUENCY ADJUSTER
SYNC GATE TIMING GENERATOR
1
RECIN
2
MUL
3
FADJ1
4
FADJ2
5
GND1
6
AMPOUT
7
GND
8
SCMPIN
9
DET
10
VCO
11
PBOUT
12
SGADJ
13
SGC
14
PALPIN
15
DIV
16
SYNCIN
RECOUT
BA7207AK (SQFP44)
ABELO
CREF2
CREF1
LAIN
VCC
LAO
N.C.
N.C.
N.C.
33
32
31
30
29
28
27
26
25 VCC
24
23
TRAP
34 LIM MODE CONTROL
CTL
BWL
LAO
VCC
CTL
22
CREF3
PALRIN
35 PAL SCM
21
RECH
VREG
36
VREG
20
PBIN
N.C.
37
19
N.C.
x 4O
N.C.
38
x2
P
2.2MHz BPF P R
x2
R
P LIM
R EQ 1.1MHz BPF
P 18 R 17 BWL
39
N.C.
RECIN
40 R
4.3MHz BPF--A
R BELL P
P
4.3MHz BPF--B
PB SYNC GATE
/4
REC SYNC GATE
16 SYNC GATE TIMING GENERATOR
SYNCIN
N.C.
41
FREQUENCY ADJUSTER
DET
VCO
15
N.C.
MUL
42 SCM PAL
14
DIV
FADJ1
43
13
PALPIN
FADJ2
44
12
SGC
1
GND1
2
AMPOUT
3
GND
4
N.C.
5
SCMPIN
6
N.C.
7
DET
8
N.C.
9
VCO
10
PBOUT
11
SGADJ
2
Video ICs
BA7207AS / BA7207AK
*Pin descriptions
Pin No. Pin name 1 (40) RECIN Function
Recording system input. Input the REC system chroma signal. PB sync gate output. Test pin. Outputs the chroma signal after it is multiplied by four and passed through the sync gate. Normally connected to VCC to prevent interference. Filter fo adjustment pin 1. Used to adjust fo for the equalizer, 1.1MHz BPF and 2.2MHz BPF. Connect a resistor and variable resistor from this pin to GND. Filter fo adjustment pin 2. Used to adjust fo for the bell filter, 4.3MHz BPF-A and 4.3MHz BPF-B. Connect a resistor and variable resistor from this pin to GND. Ground. PB system preamplifier output.
Pin No. Pin name 17 (18) 18 (20) BWL PBIN
Function
Chroma killer mode setting . "L" sets the IC in chroma killer mode. PB system input . Input chroma signal for the PB system. REC / PB mode switch. Set to open or "H" for REC mode, "L" for PB mode. Bias terminal for the limiter amplifier before x 2.
2 (42)
MUL
19 (21) RECH
3 (43)
FADJ1
20 (22) CREF3 Connect to GND via a capacitor.
4 (44)
FADJ2
21 (23)
CTL
SECAM / PAL output switch. Selects the signal output for the REC / PB terminal. Set to open or "H" for SECAM output mode, "L" for PAL mode. Limiter amplifier output. Test pin. Outputs the amplitude-limited chroma signal. Normally connected to VCC to prevent interference. Power supply. Limiter amplifier input. Input the de-emphasised chroma signal. Limiter amplifier bias pin 1.
5 (1)
GND1
22 (24)
LAO
6 (2) AMPOUT Connect to GND via a variable resistor to adjust
the level, and input to pin 8.
23 (25) 24 (27)
VCC LAIN
7 (3) 8 (5)
GND SCMPIN
Ground. PB system output amplifier input. Input the level-adjusted PB system SECAM chroma signal. Phase comparator output. Connect to GND via a RC LPF to obtain the error voltage. VCO oscillator frequency control pin. The error voltage is input via a resistor. Connected to GND via free-running frequency setting resistor. PB system output.
25 (29) CREF1 Connect to GND via a capacitor.
REC BELL output. When in REC mode, de-emphasised chroma signal is output via REC BELL. When in PB mode, the PB system chroma signal is output after being multiplied by four. Limiter amplifier bias pin 2.
9 (7)
DET
26 (31) ABELO
10 (9)
VCO
27 (32) CREF2 Connect to GND via a capacitor. 28 (33) RECOUT REC system chroma signal output. 29 (34) TRAP
TRAP connection. Connect TRAP that rejects spurious signal component after x 2 multiplication. PAL REC system input. REC system output.
11 (10) PBOUT Outputs the PB system chroma signal.
Fine adjustment for the sync gate phase. The voltage from a resistor divider is used for fine adjustment of the gate phase of the sync gate. Normally open. Sync gate timing output. Test pin. Outputs the REC sync gate timing. Normally open. PAL PB system input.
12 (11) SGADJ
30 (35) PALRIN PAL REC system chroma signal input.
Regulated voltage output. Output for the regulated 2.5V reference voltage used for internal biasing. Connect to GND via a bypass capacitor. x 4 multiply output. Test pin. Outputs the chroma signal after it is multiplied by four. Normally connected to VCC to prevent interference. BA7207AK pin numbers are given in brackets.
13 (12)
SGC
31 (36) VREG
14 (13) PALPIN Input chroma signal for the PAL PB system.
Divide-by-four divider output. Test pin. Outputs the chroma signal after it has been divided by four. Normally connected to VCC to prevent interference. Delayed sync signal input.
15 (14)
DIV
32 (38)
x 40
16
SYNCIN Input the synchronously-separated composite
3
Video ICs
BA7207AS / BA7207AK
*Input / output circuits
1pin (40pin) 2pin (42pin) 3pin (43pin)
VCC VCC VCC 40k RECIN 40k GND GND MUL GND VCC VCC
FADJ1
GND
4pin (44pin)
VCC
5pin (1pin)
6pin (2pin)
VCC VCC VCC GND1 FADJ2 GND AMPOUT 5k GND
GND
GND
7pin (3pin)
8pin (5pin)
9pin (7pin)
VCC 20k GND SCMPIN GND 30k GND SCMPIN
VCC 20k
30k GND
4
Video ICs
BA7207AS / BA7207AK
10pin (9pin)
VCC 5k 12k VCO
11pin (10pin)
VCC
12pin (11pin)
VCC VCC 50k VCC SGADJ 100k
GND
PBOUT 2.2k GND GND
GND
50k GND
13pin (12pin)
14pin (13pin)
15pin (14pin)
VCC
VCC 10k SGC 10k GND PALPIN
VCC VCC 20k
30k GND
DIV
GND
16pin
17pin (18pin)
VCC VCC 50k 15k
18pin (20pin)
VCC 20k PBIN 20k
SYNCIN 35k GND
BWL
GND GND
19pin (21pin)
VCC 50k RECH
20pin (22pin)
VCC
21pin (23pin)
VCC 50k
CREF3
CTL
GND
GND
GND
5
Video ICs
BA7207AS / BA7207AK
22pin (24pin)
VCC
23pin (25pin)
24pin (27pin)
VCC
VCC VCC
LAIN 2k
LAO
VCC
GND
GND
GND
25pin (29pin)
VCC
26pin (31pin)
VCC
27pin (32pin)
VCC
2k CREF1 30k ABELO GND
VCC CREF2
2k 30k
GND 1.8k
GND
GND
GND
28pin (33pin)
VCC
29pin (34pin)
VCC VCC 560 TRAP
30pin (35pin)
VCC 20k PALRIN 30k
RECOUT 1.8k GND
200 GND GND
31pin (36pin)
VCC
32pin (38pin)
VCC VCC VCC
VREG x 4O 3k GND 5.3k GND 3k
Pin numbers in parentheses are for the BA7207AK.
6
Video ICs
BA7207AS / BA7207AK
*Electrical characteristics (unless otherwise noted, Ta = 25C, VCC = 5.0V)
Parameter [Total device] REC mode supply current PB mode supply current Regulator voltage [Sync-gate block] VCO free-running frequency Capture range "H" Capture range "L" Lock range "H" Lock range "L" [REC system] RECOUT output amplitude Unwanted spectrum rejection 4MHz component 3MHz component 2MHz component Output switch voltage gain Output switch frequency characteristic Output switch crosstalk 1 Output switch crosstalk 2 [PB system] PB output amplitude Unwanted spectrum rejection 3MHz component 2MHz component 1MHz component Output switch voltage gain 1 Output switch frequency characteristic 1 Output switch crosstalk 1 Output switch voltage gain 2 Output switch frequency characteristic 2 Output switch crosstalk 2 RECIN crosstalk [Control system] High level voltage Low level voltage VH VL 2.5 -- -- -- -- 1.5 V V Pins 14, 17, 19, 21 and 30 (Pins 13,18,21,23 and 35) Pins 14, 17, 19, 21 and 30 (Pins 13,18,21,23 and 35) HDP3 HDP2 HDP1 GP1 fP1 CTP1 GP2 fP2 CTP2 CTRIN -- -- -- 5 -1 -- -1 -1 -- -- -- -- -- 6 0 - 60 0 0 - 60 - 40 - 35 - 35 - 35 7 1 -- 1 1 -- - 30 dB dB dB dB dB dB dB dB dB dB V18 = 25mVP-P, 1.0715MHz V18 = 25mVP-P, 1.0715MHz V18 = 25mVP-P, 1.0715MHz V8 = 0.3VP-P, 4.3MHz V8 = 0.3VP-P, 5MHz / 100kHz V8 = 0.3VP-P, 4.3MHz V14 = 0.3VP-P, 4.43MHz V14 = 0.3VP-P, 5MHz / 100kHz V14 = 0.3VP-P, 4.43MHz V1 = 0.5VP-P, 4.286MHz VPB 202.5 270.0 337.5 mVP-P Cyan level (cyan frequency) HDR4 HDR3 HDR2 GRS fRS CTR1 CTR2 -- -- -- -1 -1 -- -- -- -- -- 0 0 - 60 - 60 - 25 - 25 - 25 1 1 -- -- dB dB dB dB dB dB dB V1 = 170mVP-P, 4.286MHz V1 = 170mVP-P, 4.286MHz V1 = 170mVP-P, 4.286MHz V30 = 0.3VP-P, 627kHz V30 = 0.3VP-P, 5MHz / 100kHz V18 = 25mVP-P, 1.0715MHz V30 = 0.3VP-P, 627kHz VREC 187.5 250.0 312.5 mVP-P Cyan level (cyan frequency) fosc CRH CRL LRH LRL 13.8 15.625 17.4 1.8 -- 2.2 -- -- -- -- -- -- - 1.8 -- - 2.2 kHz kHz kHz kHz kHz Delayed sync input Delayed sync input Delayed sync input Delayed sync input IREC IPB VREG 39.2 46.9 2.38 56.0 67.0 2.53 72.8 87.1 2.68 mA mA V REC mode PB mode Symbol Min. Typ. Max. Unit Conditions
Measurement circuit
Fig.1 Fig.1 Fig.1
Fig.1 Fig.1 Fig.1 Fig.1 Fig.1
Fig.1
Fig.1 Fig.1 Fig.1 Fig.1 Fig.1 Fig.1 Fig.1
Fig.1
Fig.1 Fig.1 Fig.1 Fig.1 Fig.1 Fig.1 Fig.1 Fig.1 Fig.1 Fig.1
Fig.1 Fig.1
BA7207AK pin numbers are given in brackets.
7
Video ICs
BA7207AS / BA7207AK
Parameter [Filter block] 1.1MHz BPF characteristic 1.1MHz voltage gain 0.5MHz voltage gain 3.2MHz voltage gain 4.3MHz BPF - A characteristic 4.3MHz voltage gain 3.2MHz voltage gain 5.5MHz voltage gain
Symbol
Min.
Typ.
Max.
Unit
Conditions
Measurement circuit
GF11 GF12 GF13
- 2.8 - 6.5 --
0.7 - 3.0
4.2 0.5
dB dB dB
V18 = 25mVP-P, 1.0715MHz V18 = 25mVP-P, 0.5MHz V18 = 25mVP-P, 3.2145MHz
Fig.1 Fig.1 Fig.1
- 35.0 - 26.0
GF31 GF32 GF33
- 11.3
- 7.8
- 4.3 - 9.1 - 7.0
dB dB dB
V1 = 500mVP-P, 4.286MHz V1 = 500mVP-P, 3.2MHz V1 = 500mVP-P, 5.5MHz
Fig.1 Fig.1 Fig.1
- 16.1 - 12.6 - 14.0 - 10.5
REC BELL + 4.3MHz BPF - A characteristic 4.3MHz voltage gain 4.1MHz voltage gain 4.5MHz voltage gain GRB1 GRB2 GRB3 - 0.7 - 7.0 - 7.2 2.8 - 3.5 - 3.7 6.3 0 - 0.2 dB dB dB V1 = 170mVP-P, 4.286MHz V1 = 170mVP-P, 4.1MHz V1 = 170mVP-P, 4.5MHz Fig.1 Fig.1 Fig.1
PB BELL + 4.3MHz BPF - A characteristic 4.3MHz voltage gain 4.1MHz voltage gain 4.5MHz voltage gain REC EQ + 1.1MHz BPF characteristic 1.1MHz voltage gain 1.0MHz voltage gain 1.2MHz voltage gain PB EQ + 1.1MHz BPF characteristic 1.1MHz voltage gain 1.0MHz voltage gain 1.2MHz voltage gain GPE1 GPE2 GPE3 2.5 - 5.1 - 8.9 6.0 - 1.6 - 5.4 9.5 1.9 - 1.9 dB dB dB V18 = 25mVP-P, 1.0715MHz V18 = 25mVP-P, 1.0MHz V18 = 25mVP-P, 1.2MHz Fig.1 Fig.1 Fig.1 GRE1 GRE2 GRE3 - 4.0 4.1 6.7 - 0.5 7.6 10.2 3.0 11.1 13.7 dB dB dB V18 = 95mVP-P, 1.0715MHz V18 = 95mVP-P, 1.0MHz V18 = 95mVP-P, 1.2MHz Fig.1 Fig.1 Fig.1 GPB1 GPB2 GPB3 - 20.9 - 17.4 - 13.9 - 16.2 - 12.7 - 15.3 - 11.8 - 9.2 - 8.3 dB dB dB V1 = 800mVP-P, 4.286MHz V1 = 800mVP-P, 4.1MHz V1 = 800mVP-P, 4.5MHz Fig.1 Fig.1 Fig.1
*Guaranteed design parameters (unless otherwise noted, Ta = 25C, VCC = 5.0V, delayed sync input)
Parameter REC sync-gate phase PB sync-gate phase REC sync-gate amplitude PB sync-gate amplitude Symbol TDR TDP TWR TWP Min. 1.3 0.5 4.9 6.1 Typ. 2.4 1.6 5.2 6.4 Max. 3.5 2.7 5.5 6.7 Unit s s s s Conditions DIV (pin 14 / pin 15), REC mode MUL (pin 2 / pin 42), PB mode DIV (pin 15 / pin 14), REC mode MUL (pin 2 / pin 42), PB mode
The pin numbers in brackets are for the BA7207AS and the BA7207AK respectively.
8
Video ICs
BA7207AS / BA7207AK
*Reference design data Ta = 25C, VCC = 5.0V, fo (REC BELL) = 4.286MHz, fo (PB EQ) = 1.0715MHz) (unless otherwise noted,
Parameter 1.1MHzBPF 1.1MHz gain 0.5MHz suppression ratio 3.2MHz suppression ratio Groupe delay time 2.2MHzBPF 2.2MHz gain 1.1MHz suppression ratio 3.2MHz suppression ratio Groupe delay time 4.3MHz BPF - A 4.3MHz gain 3.2MHz suppression ratio 5.5MHz suppression ratio Groupe delay time 4.3MHz BPF - B 4.3MHz gain 3.5MHz suppression ratio 5.2MHz suppression ratio Groupe delay time REC BELL 4.3MHz gain 4.1MHz suppression ratio 4.5MHz suppression ratio PB BELL 4.3MHz gain 4.1MHz gain 4.5MHz gain Center frequency ratio PB EQ 1.1MHz gain 1.0MHz suppression ratio 1.2MHz suppression ratio REC EQ 1.1MHz gain 1.0MHz gain 1.2MHz gain Center frequency ratio GPE1 GPE2 GPE3 dfOE -- -- -- -1 - 19.5 8.0 11.0 0 -- -- -- 1 dB dB dB % VIN = 0.3VP-P, 1.0715MHz VIN = 0.3VP-P, 1.0MHz VIN = 0.3VP-P, 1.2MHz dfOE = (fO (REC) - fO (PB) ) / fO (PB) GRE1 GRE2 GRE3 -- -- -- 19.5 - 8.0 - 11.0 -- -- -- dB dB dB VIN = 0.3VP-P, 1.0715MHz VIN = 0.3VP-P, 1.0MHz VIN = 0.3VP-P, 1.2MHz GPB1 GPB2 GPB3 dfOB -- -- -- -1 - 19.5 5.0 5.5 0 -- -- -- 1 dB dB dB % VIN = 0.3VP-P, 4.286MHz VIN = 0.3VP-P, 4.1MHz VIN = 0.3VP-P, 4.5MHz dfOB = (fO (PB) - fO (REC) ) / fO (REC) GRB1 GRB2 GRB3 -- -- -- 19.5 - 5.0 - 5.5 -- -- -- dB dB dB VIN = 0.3VP-P, 4.286MHz VIN = 0.3VP-P, 4.1MHz VIN = 0.3VP-P, 4.5MHz GF41 GF42 GF43 DF4 -- -- -- 250 9.0 - 3.0 - 3.0 300 -- -- -- 350 dB dB dB nS VIN = 0.1VP-P, 4.286MHz VIN = 0.1VP-P, 3.5MHz VIN = 0.1VP-P, 5.2MHz VIN = 0.1VP-P, 4.286MHz GF31 GF32 GF33 DF3 -- -- -- 160 7.0 - 3.0 - 3.0 210 -- -- -- 260 dB dB dB nS VIN = 0.1VP-P, 4.286MHz VIN = 0.1VP-P, 3.2MHz VIN = 0.1VP-P, 5.5MHz VIN = 0.1VP-P, 4.286MHz GF21 GF22 GF23 DF2 -- -- -- 180 - 6.0 - 25.0 - 25.0 230 -- -- -- 280 dB dB dB ns VIN = 0.3VP-P, 2.143MHz VIN = 0.3VP-P, 1.0715MHz VIN = 0.3VP-P, 3.2145MHz VIN = 0.3VP-P, 2.143MHz GF11 GF12 GF13 DF1 -- -- -- 370 1.0 - 4.0 - 30.0 420 -- -- -- 470 dB dB dB nS VIN = 0.3VP-P, 1.0715MHz VIN = 0.3VP-P, 0.5MHz VIN = 0.3VP-P, 3.2145MHz VIN = 0.3VP-P, 1.0715MHz Symbol Min. Typ. Max. Unit Conditions
9
Video ICs
BA7207AS / BA7207AK
*Measurement circuits
BA7207AS (SDIP32)
1 N 2 SW30b OSC30 OSC18 1 2 SW30a 1 2 SW18 1 N 2 SW21 1 N 2 SW19
VREG
0.01
RECOUT
Vcc 0.1 0.1 0.1 A
I23
27p Vcc
0.1
47
0.1 Vcc
0.01
47
+ 0.01
32
31
30
29
28
27
26
25
24
23
22
21
CTL MODE CONTOROL
20
19
RECH
18
17
BWL
Vreg
PAL
SCM
LIM
x2
2.2MHz BPF
x2
R
LIM
P
1.1MHz BPF
P
EQ
R
P
4.3MHz BPF - A
P R BELL R R P
4.3MHz BPF - B
PB SYNC GATE
/4
REC SYNC GATE
R
DET
VCO SCM PAL
SYNC GATE TIMING GENERATOR
FREQUENCY ADJUSTER
1
SW2 0.01 OSC1 1 2
2
3
SW3 2 1 2k VR1
8.5k 7.5k
4
SW4 2
5
6
7
8
9
10
100k
11
12
13
14
15
SW15 1 2
16
1
0.01 0.47 SW8 AMPOUT 470 470 12 560p
1 2 3
10k
100P 3.3k 1 SW16 2
3.9k
2k VR2
8.5k
4700p + 33k PBOUT SGC 0.01
V
7.5k
V
SG16
Vcc
SW14a 1
2 OSC14
Vcc
OSC8
SW14b 1 N 2
1.5V
2.5V
Fig. 1
10
Video ICs
BA7207AS / BA7207AK
BA7207AK (QFP44)
1N SW30b VCC 0.1 0.01 0.1 0.1 I23 2 REC OUT SW21 SW19 SW4b 1.5V 2.5V 1N 2 1N 2 1N 2
A
+
47 VCC
OSC30
33
27p 47
32
31
30
29
28
27
26
25
VCC
24
23
0.1
~
1 SW30a 0.01 2
34
LIM
22
MODE CONTROL
35
PAL SCM VREG 0.1 VCC
21 20 19
36 37 38 39 40
VREG
0.01 SW18 1 2
x2
2.2MHz BPF P R
x2
P
LIM
R EQ 1.1MHz BPF
P R
18 17
~
OSC18
P 4.3MHz BPF--A
R R
BELL
P 4.3MHz BPF--B
PB SYNC GATE
/4
REC SYNC GATE
0.01 OSC1
R
FREQUENCY ADJUSTER
16
P DET VCO
SYNC GATE TIMING GENERATOR
SW16 100p 1 2 SG16
~
41 42
15 14
1
SW2 2
43 44
SW3 SW4 2
2k VR2 8.5k 7.5k
SCM PAL
13
0.01
3.9k
12
1
SW14a 2 1
SW15 2
VCC
1
2
1
~
OSC14
3.3k
2k VR1 8.5k 7.5k
1
470
2
3
4
0.01
5
6
7
8
100k
9
10
11
VCC
SW8 1 2 3
10k + 0.47 33k 4700p
PB SG OUT 470 12 560p
~
OSC8
AMP OUT
PB OUT
SGC
REC SG OUT
Fig. 2
11
Video ICs
BA7207AS / BA7207AK
*Circuit operation (REC) (1) Recording system
The input to REC IN is passed through the 4.3MHz BPF-A to remove unwanted frequency components, and is flattened by REC BELL which has an anti-bell characteristic. The flattened signal is wave-shaped by the limiter amplifer, and processed by the divide-by-four and sync gate circuits. Finally, unwanted frequency components are removed by the 1.1MHz BPF and the REC EQ prepares the signal for recording playback and the signal is output on REC OUT. Refer to Fig. 3.
Composite video signal 1 100pF 4.3MHz BPF - A 40 REC BELL 26 24 31 LIMAMP 27 /4 REC SYNC GATE RECOUT
AMP
1.1MHz BPF
REC EQ
28
(
)
(
)
(
)
BA7207AS (BA7207AK)
(
33
)
Fig. 3
(2) Playback system (PB) The input to PB IN is passed through the 1.1MHz BPF to remove unwanted frequency components, and is flattened by the PB EQ circuit. The amplitude of the flattened signal fixed by the 1st-stage limiter amplifier, and the frequency is multiplied by four by the multiplier circuit. Unwanted frequency components generated by the multiplier circuit are removed by the 2.2MHz BPF and 4.3MHz BPF-A. The signal is wave-shaped by the limiter amplifier, and has gate applied to it by the sync gate circuit then is passed through the 4.3MHz BPF-B to remove unwanted frequency components. The PB BELL circuit restores the original bell characteristic and the signal is output on PB OUT. Refer to Fig. 4.
RF chroma signal LPF fc 2.2MHz 18
AMP
1.1MHz BPF
PB EQ
LIMAMP
x2
(
20
) )
LIMAMP PB SYNC GATE 4.3MHz BPF - B PB BELL BA7207AS (BA7207AK)
2.2MHz BPF
x2
4.3MHz BPF - A
26
(
24
31
PBOUT
AMP
6 2
8
TRAP
AMP
11
(
27
)
(
)
(
5
)
(
10
)
Fig. 4
(3) Sync gate timing circuit REC and PB SYNC gate operation is as follows. The gate closes closes in synchronous with the SYNC IN input pulse during the synchronous signal pulse (SYNC) horizontal scan interval (64s period). During vertical retrace (32S period), the input pulse period becomes shorter than the horizontal scan interval. This is detected by the builtin vertical synchronous detector circuit which closes the gate. Refer to Fig. 5.
Horizontal scan interval 64s 4s SYNCIN 32s Vertical retrace interval
REC / PBOUT ,,,,,,
,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,, ,,,,,,
,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,, ,,,,,,,,,,
Fig. 5
12
Video ICs
BA7207AS / BA7207AK
*Application examples
BA7207AS (SDIP32)
PAL REC C. REC C OUT VCC SCM / PAL REC / PB
100 0.1 0.01 27p 47 0.01 0.1 0.1 0.01 0.01 + 47 0.1
LPF
PBIN B/W
0.01
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vreg
MODE CONTOROL
PAL
SCM
LIM
R x2
2.2MHz BPF
P
1.1MHz BPF
x2
LIM
P
EQ
R
P
4.3MHz BPF - A
P R BELL R R P
4.3MHz BPF - B
PB SYNC GATE
/4
REC SYNC GATE
R
DET
VCO
SYNC GATE TIMING GENERATOR
SCM PAL
FREQUENCY ADJUSTER
1
2
3
VR1 BELL fo ADJ EQ fo ADJ
4
5 VR2
PBOUT LEVEL
6
VR3
7
8
0.01
9
10
100k
11
0.01
12
13
14
0.01
15
16
100p
4700p
7.5k

2KVR x 2
100p
SYNC IN PALPB C PB C OUT RECIN
10k 1k 12 560p 0.47
7.5k
33k
To cancel the temperature characteristic of the ID, the resistors marked with asterisks should be of the metal film, and have a
temperature coefficient 100ppm / C. : Test pin. Connect to VCC if unused. The 100pF capacitor connected to pin 16 is intended to reduce temperature disper of the gate phase.It should have a static capacitance tolerance of 10% or Ic and a temperature coefficient of 30ppm / C ( - 55C to + 125C) A (CG).
Fig. 6
13
Video ICs
BA7207AK (QFP44)
BA7207AS / BA7207AK
100 0.01 0.01 0.1 0.01 0.1 0.01 + 47
PAL REC C. REC C OUT. VCC SCM/PAL REC/PB PBIN B/W
33
32
31
30
29
28
27
26
25
VCC
24
23
34
LIM
22
0.1
MODE CONTROL
47
35
PAL SCM
21
0.01
27p 0.1
36 37
Vreg
20 19
LPF
38 39
100p
x2
2.2MHz BPF P R
x2
P
LIM
R EQ 1.1MHz BPF
P R
18 17
P 4.3MHz BPF--A
R R
BELL
P 4.3MHz BPF--B
PB SYNC GATE
/4
REC SYNC GATE
40 41
R FREQUENCY ADJUSTER
16
P DET VCO
SYNC GATE TIMING GENERATOR
15
100p
42 43
BELL of ADJ EQ of ADJ SCM PAL
14
0.01
13 12
VR1
44
VR2
2k VR

2k VR
PBOUT LEVEL
7.5k
7.5k
1
2
VR3
3
4
0.01
5
6
7
8
100k
9
10
11
10k 1k 12 + 0.47 580p 4700p
33k
0.01
SYNC IN PALPB C. PB C OUT RECIN
To cancel the temperature characteristic of the ID, the resistors marked with asterisks should be of the metal film, and have a
temperature coefficient 100ppm / C. : Test pin. Connect to VCC if unused. The 100pF capacitor connected to pin 16 is intended to reduce temperature disper of the gate phase.It should have a static capacitance tolerance of 10% or Ic and a temperature coefficient of 30ppm / C ( - 55C to + 125C) A (CG).
*Control pin logic
Pin REC / PB setting switch RECH (19pin / 21pin) Output select switch Chroma killer switch CTL (21pin / 23pin) BWL (17pin / 18pin) Low PB PAL
Fig. 7
High (Open) REC SECAM NORMAL
Chroma killer
(BA7207AS / BA7207AK)
14
Video ICs
BA7207AS / BA7207AK
*Operation notes (1) Equalizer fo adjustment
Set to PB mode and input a 25mVP-P, 1.0715MHz sine wave to PBIN. Adjust the variable resistor connected between FADJ1 and GND to maximize the REC OUT output. This adjustment also adjusts the 1.1MHz and 2.2MHz band-pass filters. The value of the variable resistor must be at least 2k. If it is less than this, adjustment may not be possible. (2) Bell filter fo adjustment Set to REC mode and input a 170mVP-P, 4.286MHz sine wave to RECIN. Adjust the variable resistor connected between FADJ2 and GND to maximize the AMP OUT output. This adjustment also adjusts the 4.3MHz and 4.3MHz A and B band-pass filters. The value of the variable resistor must be at least 2k. If it is less than this, adjustment may not be possible. (3) Test pins The MUL, DIV, LAO and 4XO pins are test terminals. By connecting these pins to GND via a 3.6k resistor, it is possible to monitor there waveforms. When unused, connect these pins to VCC to prevent interference. (4) REC / PB input levels The frequency characteristics of the built-in filters can change. For this reason use the following input signal levels: RECIN: 540mVP-P + / - 6dB (cyan level) PBIN: 75mVP-P + / - 6dB (cyan level) (5) Capacitor connected to VREG Use a ceramic with a static capacitance of 0.1F. The filter may not operate correctly with other capacitance values.
(6) PBIN input If there is a chroma component imposed on the FM brightness signal, use a low-pass filter (with an fc of about 2.2MHz) to remove the FM brightness signal component, and ensure that only the chroma component is input to PBIN. (7) RECIN input In the case of composite video input, connect a 100pF capacitor to ensure that only the chroma component is input to RECIN. (8) Sync-gate phase adjustment Perform fine adjustment of the sync-gate phase by applying a voltage to the SGADJ terminal, or using a resistor divider connected between VCC and GND. The adjustment sensitivity is shown in Fig. 6. SGADJ pin voltage when open: VSGADJ = 2.5V Input impedance Z = 125k
GATE PHASE ADJUSTMENT: TDR (S)
+ 3.2
0
0.32S / 0.1V
- 3.2
1.5
2.5
3.5
SGADJ PIN APPLY VOLTAGE: VSGADJ (V)
Fig. 8 Sync-gate phase
15
Video ICs
BA7207AS / BA7207AK
*Electrical characteristic curves
1.3 REC / PB BELL FREQUENCY: fo (MHz) REC / PB EQ FREQUENCY: fo (MHz) 6PIN REC BELL FREQUENCY: fo (MHz) 5.5 4.40 Conditions VCC = 5.0V fo = 4.286MHz V = 170mVP-P 1.2 4.35 5.0 4.30
1.1
4.5
4.25
fo
1.0
4.0
4.20
0.9
7.5
8.0
8.5
9.0
9.5
3.5
4.15 7.5 8.0 8.5 9.0 9.5 FADJ2 RESISTANCE VALUE: RADJ2 (k)
0
100
200
300
400
500
FADJ1 RESISTANCE VALUE: RADJ1 (k)
1PIN REC IN LEVEL: VIREC (mVP-P)
Fig. 9 REC / PB EQ fO frequency adjustment range
Fig. 10 REC / PB BELL fO frequency adjustment range
Fig. 11 REC / BELL fO frequency variation
1.09 28PIN PB EQ FREQUENCY: fo (MHz) Conditions VCC = 5.0V fo = 1.0715MHz V = 25mVP-P
- 10 - 20 REC OUT LEVEL: VOREC (dBm) - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100
Fundamental frequency 2MHz component component 3MHz component 4MHz component
- 10 RECIN f = 4.286MHz V = 170mVP-P - 20 PB OUT LEVEL: VOPB (dBm) - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 5.0 - 110 0
Fundamental frequency component
1.08
PB IN f = 1.0715MHz V = 25mVP-P
8MHz component 6MHz component
1.07 fo
1.06
1MHz component
3MHz component
5MHz component
7MHz component
1.05
2MHz component
1.04
0
20
40
60
80
100
- 110 0
1.0
2.0
3.0
4.0
1
2
3
4
5
6
7
8
9
10
18PIN PB IN LEVEL: VIPB (mVP-P)
FREQUENCY: f (MHz)
FREQUENCY: f (MHz)
Fig. 12 PB EQ fO frequency variation characteristics
Fig. 13 REC OUT spurious characteristics
Fig. 14 PB OUT spurious characteristics
16
Video ICs
BA7207AS / BA7207AK
*External dimensions (Units: mm)
BA7207AS BA7207AK
28.0 0.3 32 17 8.4 0.3 14.0 0.3 10.0 0.2 33 23 14.0 0.3 10.0 0.2 34 22
0.51Min.
1
16 10.16
3.2 0.2 4.7 0.3
44 1 11
12
0.3 0.1
2.15 0.1
0.05
1.778
0.5 0.1
0 ~ 15
0.8
0.35 0.1
0.15
SDIP32
QFP44
1.2 0.15 0.1
17

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